Serial data must be transmitted across wired media. The transmit and receive sections include chips wired to one another and card-to-card interconnects. The transmission media can be a combination of a printed circuit board, connectors, backplane wiring, fiber or cable. The interconnect can include its own power, data and clocking sources or may derive these functions from a host module. Such data has typically been transmitted through a parallel data bus, such as ISA, PCI, PCI-X and the like. One drawback of such parallel links is the moderate rate of data transmission as compared to improved microprocessor performance, resulting in data transfer bandwidths that typically outpace I/O transfer rates. Also, the ASIC I/O count is high. In addition, the system integration I/O count using a parallel data bus is high. Finally, the overall system cost associated with the use of the parallel data bus tends to be high.
A clock and data recovery system recovers a clock signal from a high speed data stream. The system uses high speed, low power clock recovery circuits. Analog techniques for recovery of the clock signal have drawbacks. Among them is the need to use a low pass filter to store a control voltage. Another drawback is that they only achieve recovery over a very small bandwidth relative to the data rate. Some have achieved clock and data recovery by use of an oscillator locked to an incoming signal. Others have used frame synchronization using QAM (queued access method) modulation. Still others have used a method of clock frequency multiplication. None of these prior art systems utilizes a clock and data recovery based on oversampling, which is a technique that is used to improve the signal to noise ratio in transmission systems by spreading out the noise induced by the digital-to-analog converter over a greater frequency range.
Typical clock/data recovery based on a single sample per bit, requires a phase/frequency detector. Also, oversampling with two samples per bit typically places one sample in the center of the bit and one on the edge, detecting 50/50 zeros and ones from edge samples when centered. This type of oversampling depends on the statistical detection of the edge samples and, therefore, has a non-zero probability of making an incorrect decision about the position of the edge in the presence of random phase noise. The receiver structure performs clock and data recovery (CDR) on the incoming serial bit stream. The quality of this operation is a dominant factor for the bit error rate (BER) performance of the system.